Introduction to Digital Design

Digital Design Chart

This chart must be always in the mind of digital designer because it explains the relation between every level where you must know in which level you are working on and which level will you go on later

Digital Logic Design

Digital Systems

A Digital System is an interconnection of digital modules, to understand operation of each digital module, it is necessary to have a basic knowledge of digital circuits and their logic function.

DigitalSystem
credits:quora.com

Number set

Number set defines a set of values used to represent quantity

Register Transfer Level Design

Finite\Algorithmic State Machines

FSM Types
credits:Prof.PaulFranzon

Computer Architecture (System & Algorithmic Level)

Digital ASIC Design

this stage we transform logic circuits to real circuits using transistors

Memories

Static Random Access Memory

SRAM Cell structure
credits:Prof.Karim Abbas

schematic above is a representation of a two inverters connected to each other which they can save their data forever where M1,M2 forms an inverter its output is Q && M3,M4 forms an another inverter its output is Q' we don't use here a transmission gate which passes pure VDD or zero but we use nmos only in favour of area

transmission gate structure

Dynamic Random Access Memory

Dram is the bulk memory you will find in any digital system like your pc also it is the most fast and high dense read/write memory, it can also be synchronous which we call SDRAM and can be asynchronous. we have 3 types of DRAM in terms of structure

1. 4-Transistor Structure
2. 3-Transistor Structure
3. 1-Transistor Structure(most practically used but with many problems)

4-Transistor

when we write we drive first bit lines assume \(BL'=V_{DD}\) and \(BL=0\) then drive wordline assume we drive it with VDD then 0V will move to point Q and VDD will move to point Q' then disable word line by 0V
we will notice that Q' will make M1 turn on and then Q=0V and Q will turn M3 off which Makes Q'=VDD but notice that M3(Q) and M6(WL) are off but so VDD is at high impedance node where we keep its value at this node on a capacitor formed at this node